Tools:

Description:

Complete RTL-to-GDSII implementation of FSM-based toll booth controller with automated toll collection, account verification, and barrier control. Covers full ASIC design flow including synthesis, formal verification, DFT insertion, physical design, and tape-out ready GDSII generation.

Key Responsibilities:

• Designed FSM-based toll booth controller with 7 states (IDLE, READ_ID, CHECK_BALANCE, CHARGE_ACCOUNT, OPEN_GATE, CLOSE_GATE, REJECT_TRANSACTION)
• Implemented hierarchical RTL design with vehicle_interface, account_balance (16×16-bit RAM), and barrier_ctrl submodules
• Performed multi-constraint synthesis (minimum area, minimum timing, intermediate) with timing/power/area trade-off analysis
• Executed complete physical design flow including floorplanning (UF 0.5/0.8), placement, clock tree synthesis, and detailed routing
• Achieved 100% FSM coverage through comprehensive testbench with randomized stress testing and timeout scenarios
• Implemented DFT with scan chain insertion achieving >95% fault coverage with <2% area overhead

Technical Challenges:

• Resolving setup violations (-0.606ns) after placement through clock tree optimization
• Balancing area-timing-power trade-offs across three synthesis strategies
• Managing routing congestion in high utilization (0.8) designs while meeting timing
• Achieving formal equivalence across all synthesis corners and DFT insertion

Results:

• 100% functional verification coverage across all FSM states and transitions
• 100% formal equivalence proven between RTL and netlist using Conformal
• Zero setup/hold violations in post-route STA (100% timing check coverage)
• DFT area overhead: 0.76% (UF 0.5), 2.06% (minimum timing)
• Power consumption: 0.536mW (min area), 1.777mW (min timing) @ 65nm
• Clean DRC/LVS verification - tape-out ready GDSII generated
• Clock tree synthesis improved setup slack by 0.681ns (UF 0.5)

Skills Demonstrated:

Tools:

Description:

Complete VLSI design and characterization of 4-bit True Single Phase Clock (TSPC) flip-flop in 65nm technology, featuring comprehensive pre-layout and post-layout analysis with full physical verification

Key Responsibilities:

• Designed 4-bit multibit TSPC flip-flop circuit with shared clock distribution for area and power optimization
• Implemented transistor sizing methodology based on FO4 (Fan-Out of 4) for optimal speed-power tradeoff
• Created physical layout (2.6µm × 9.16µm) with multi-layer metal routing and via optimization
• Performed parasitic extraction and post-layout simulation for accurate performance characterization
• Conducted comprehensive DRC/LVS verification achieving zero violations for fabrication readiness

Technical Challenges:

• Managing dynamic node charge leakage and noise sensitivity in TSPC design
• Achieving timing closure with 35ps degradation from parasitic RC effects
• Balancing multibit shared logic for 40% area reduction while maintaining performance
• Meeting strict 65nm design rules across Metal1/2/3 layers with via stacking

Results:

• Average propagation delay: 187.55ps (pre-layout), 222.76ps (post-layout)
• Power consumption: 39.7nW/bit @ 100MHz (pre-layout), 60.2nW/bit (post-layout)
• Total layout area: 23.816µm² for 4-bit implementation
• Achieved 40% area savings vs single-bit flip-flops through multibit architecture
• Clean DRC/LVS verification with zero violations - fabrication ready

Skills Demonstrated:

Tools:

Description:

Multi-level cache hierarchy with MSI (Modified-Shared-Invalid) coherence protocol featuring two processors with private L1 caches, shared L2 cache, and bus-based snooping mechanism

Key Responsibilities:

• Designed MSI state machine with transient states (ISD, IMD, SMD)
• Implemented write-through policy for P1 with immediate memory updates
• Developed bus arbiter with priority-based scheduling and snooping protocol
• Created 2-way set associative caches (L1: 1KB, L2: 8KB) with LRU replacement

Technical Challenges:

• Managing transient states during concurrent cache operations
• Ensuring coherence across multiple cache levels with minimal latency
• Implementing efficient bus arbitration to prevent deadlocks

Results:

• 98% cache hit rate for L1 caches
• Zero coherence violations across 1000+ test scenarios
• 7-cycle memory access latency maintained

Skills Demonstrated:

Tools:

Description:

IoT-based fire alarm system with gas/smoke detection for early warning and emergency response

Key Responsibilities:

• Designed sensor integration circuit
• Implemented wireless communication protocol
• Developed alert notification system
• Tested system reliability under various conditions

Technical Challenges:

• Minimizing false alarms while maintaining high sensitivity
• Ensuring reliable wireless communication in emergency scenarios
• Power optimization for continuous operation

Results:

• 98% detection accuracy
• Response time under 2 seconds
• Successfully deployed in test environment

Skills Demonstrated:

Tools:

Description:

Autonomous robot with obstacle avoidance, wireless control, and camera integration for surveillance

Key Responsibilities:

• Developed autonomous navigation algorithm
• Integrated ultrasonic sensors for obstacle detection
• Implemented wireless control interface
• Configured camera module for real-time video streaming

Technical Challenges:

• Optimizing pathfinding algorithm for real-time performance
• Balancing motor control for smooth movement
• Managing multiple sensor inputs simultaneously

Results:

• 95% obstacle avoidance success rate
• Wireless range of 50 meters
• Real-time video streaming at 30fps

Skills Demonstrated:

Tools:

Description:

Router architecture RTL design with efficient packet routing and verification testbenches

Key Responsibilities:

• Designed router architecture in Verilog
• Created parameterized RTL modules
• Developed comprehensive verification testbenches
• Performed functional simulation and debugging

Technical Challenges:

• Implementing efficient arbitration logic
• Handling packet priority and congestion
• Meeting timing requirements for high-speed operation

Results:

• Achieved 1 Gbps throughput
• 100% functional coverage
• Zero critical timing violations

Skills Demonstrated:

Tools:

Description:

Complete physical design implementation from RTL-to-GDS flow with timing closure and sign-off

Key Responsibilities:

• Performed floorplanning and power planning
• Executed placement and routing
• Achieved timing closure through optimization
• Conducted physical verification (DRC/LVS)

Technical Challenges:

• Meeting aggressive timing constraints
• Minimizing power consumption
• Resolving complex routing congestion issues

Results:

• Successfully met all timing constraints (setup/hold)
• 30% power reduction through clock gating
• Clean DRC/LVS with zero violations

Skills Demonstrated: