Shrishail Dolle

About Me

I am a passionate M.Tech student specializing in VLSI and Embedded Systems at Indraprastha Institute of Information Technology, Delhi, with a strong foundation in digital design, physical design, and ASIC implementation. My academic and project work spans the complete VLSI design cycle—from RTL design and verification using Verilog and SystemVerilog to physical implementation, timing closure, and GDSII tape-out.

With hands-on experience in ASIC design flow, static timing analysis, and multi-level cache coherence protocols, I've successfully executed projects such as an MSI-based cache hierarchy, a TSPC multibit flip-flop in 65nm CMOS, and an end-to-end Smart Toll System from RTL to GDSII. I am proficient in industry-standard EDA tools including Fusion Compiler, PrimeTime, and Xilinx Vivado, and I continuously explore emerging areas such as IoT, low-power design, and memory subsystem optimization.

Driven by curiosity and precision, I thrive on translating complex digital architectures into silicon-ready implementations. Whether optimizing timing paths, designing energy-efficient circuits, or building verification environments, I aim to bridge theoretical knowledge with practical, high-impact engineering. I am actively seeking research collaborations, internships, and roles where I can contribute to cutting-edge semiconductor projects while advancing my expertise in VLSI design and verification.

Skills & Expertise

Comprehensive technical abilities across VLSI design flow, verification, and computer architecture

VLSI Design Flow

RTL coding and optimizationFSM designClock Domain Crossing (CDC)Reset synchronizationLow-power RTL designMicroarchitecture designPipeline design and optimizationData path/control path partitioningDesign for Testability (DFT)Timing constraint developmentMulti-mode multi-corner (MMMC)Floorplanning and macro placementPower planning and grid designClock Tree Synthesis (CTS)Global and detailed routingPhysical verification (DRC/LVS)Static Timing Analysis (STA)Power integrity analysisSignal integrity analysisIR drop and electromigration analysis

Digital VLSI Design

Boolean algebra and logic optimizationCombinational/sequential circuit designCMOS transistor-level designArithmetic circuit designMemory element design (flip-flops, latches)Clocking methodologiesSynchronous vs asynchronous designDynamic logic and domino circuitsSetup/hold time analysisFalse path and multicycle path identificationClock gating implementationPower gating techniquesMulti-Vt library optimizationCrosstalk analysis and preventionScan chain insertionATPG pattern generationBIST implementationJTAG boundary scan design

Computer Architecture

RISC/CISC architectureProcessor pipeline designHazard detection and resolutionBranch prediction algorithmsOut-of-order executionSpeculative executionRegister renamingInstruction-level parallelism (ILP)Cache organization strategiesCache coherence protocols (MSI, MESI, MOESI)Memory consistency modelsVirtual memory system designTLB designPrefetching algorithmsMulti-core/many-core architectureNetwork-on-Chip (NoC)Bus protocols (AMBA, AXI, AHB)Performance analysis (CPI, IPC)Power-performance tradeoff optimization

Verification

UVM/OVM methodologyConstrained random verificationFunctional coverage driven verificationAssertion-based verificationFormal verificationTransaction-level modeling (TLM)Testbench architecture designScoreboard implementationCoverage model developmentEmulation and FPGA prototypingPost-silicon validation

Programming & Scripting

Hardware Description Languages (Verilog, SystemVerilog, VHDL)C/C++PythonPerlTcl/TkShell scripting (Bash)Script automation for EDA flowsAlgorithm developmentData structure implementationObject-oriented programmingRegular expression processingBuild systems (Makefile, CMake)Version control (Git)

Analytical Skills

Timing graph analysisPower consumption estimationArea optimization techniquesYield analysis and improvementProcess variation modelingThermal analysisReliability analysis (HCI, NBTI)

EDA Tools

Synopsys: Design Compiler, Fusion Compiler, ICC2, PrimeTime, VCSCadence: Genus, Innovus, Tempus, XceliumMentor Graphics: ModelSim, QuestaXilinx VivadoCadence VirtuosoSynopsys HSPICECalibre (DRC/LVS)Apache Redhawk (Power Analysis)

Design Languages & Standards

Verilog HDLSystemVerilogVHDLUVM (Universal Verification Methodology)SVA (SystemVerilog Assertions)UPF (Unified Power Format)CPF (Common Power Format)SDC (Synopsys Design Constraints)Liberty (.lib) filesLEF/DEF formats

Tools

RTL Design & Simulation Tools

  • •Cadence: Xcelium, Incisive, JasperGold
  • •Synopsys: VCS, Verdi, VC Formal
  • •Siemens EDA: QuestaSim, ModelSim
  • •Aldec: Riviera-PRO
  • •AMD Xilinx: Vivado Simulator
  • •Icarus Verilog (Open Source)
  • •Verilator (Open Source)

Synthesis Tools

  • •Synopsys: Design Compiler, Fusion Compiler
  • •Cadence: Genus Synthesis Solution
  • •Siemens EDA: Precision RTL Synthesis
  • •Yosys (Open Source)

Physical Design Tools

  • •Synopsys: IC Compiler II (ICC2), Fusion Compiler
  • •Cadence: Innovus Implementation System
  • •Siemens EDA: Aprisa
  • •OpenROAD (Open Source)

Place & Route Tools

  • •Synopsys: IC Compiler II
  • •Cadence: Innovus, Encounter
  • •OpenROAD, OpenLane (Open Source)

Static Timing Analysis Tools

  • •Synopsys: PrimeTime
  • •Cadence: Tempus Timing Signoff Solution
  • •OpenTimer (Open Source)

Physical Verification Tools

  • •Synopsys: IC Validator
  • •Cadence: Pegasus Verification System
  • •Siemens EDA: Calibre
  • •Magic, Netgen (Open Source)

Power Analysis Tools

  • •Synopsys: PrimePower, RedHawk
  • •Cadence: Voltus IC Power Integrity Solution

Analog/Mixed-Signal Tools

  • •Cadence: Virtuoso, Spectre
  • •Synopsys: Custom Compiler, HSPICE
  • •Siemens EDA: Tanner EDA

FPGA Development Tools

  • •AMD Xilinx: Vivado, ISE, Vitis
  • •Intel FPGA: Quartus Prime
  • •Microchip: Libero SoC
  • •Lattice Semiconductor: Diamond

Verification Tools

  • •Synopsys: VCS, VC Formal, Verdi
  • •Cadence: Xcelium, JasperGold
  • •Siemens EDA: Questa
  • •Cocotb (Python testbenches)

Programming & Scripting Tools

  • •TCL/TK: For EDA tool automation
  • •Python: Pandas, NumPy, Matplotlib for analysis
  • •Perl: Legacy script processing
  • •Shell: Bash, tcsh for Unix environments
  • •Git/GitHub: Version control
  • •Docker: Environment containerization
  • •Jenkins: CI/CD automation

Layout & Visualization Tools

  • •KLayout (Open Source layout viewer)
  • •GTKWave (Open Source waveform viewer)
  • •Cadence: Virtuoso Layout Suite
  • •Synopsys: Custom Designer

Project Management Tools

  • •JIRA: Bug tracking
  • •Confluence: Documentation
  • •Slack/Teams: Team communication
  • •Notion: Project organization

Operating Systems & Platforms

  • •Linux: RHEL, CentOS, Ubuntu (Primary for EDA)
  • •Windows: For documentation and office tools
  • •Cloud Platforms: AWS, Google Cloud for compute

Education

Academic journey and professional certifications

Master of Technology in VLSI and Embedded Systems

Indraprastha Institute of Information Technology, Delhi

2025 - 2027

CGPA: 9.43/10

Professional Certification in VLSI Physical Design and Verification

Maven Silicon

Aug 2024 - Feb 2025

Grade: A+

Bachelor of Technology in Electronics and Telecommunication

Veermata Jijabai Technological Institute, Mumbai

2021 - 2024

CGPA: 8.25/10

Higher Secondary Certificate (HSC) - PCM

Sangmeshwar College, Solapur

2017 - 2019

Percentage: 78.30%

Secondary School Certificate (SSC)

Mangrule High School, Akkalkot, Solapur

2011 - 2017

Percentage: 93.40% - Demonstrated strong academic performance and developed fundamental analytical and problem-solving skills

Teaching Assistantships

Circuit Theory and Devices

Mentor: Abhishekh Kumar, IIITD

Aug 2025 - Dec 2025

Course Overview

Circuit Theory and Devices is a foundational course covering fundamental principles of electrical circuits, network analysis, and semiconductor devices. The course encompasses DC/AC circuit analysis, network theorems, transient analysis, diode characteristics, transistor configurations, and amplifier design.

Key Responsibilities

  • •Laboratory Instruction: Conducted hands-on laboratory sessions for students, demonstrating proper setup and operation of oscilloscopes, function generators, multimeters, power supplies, and other electronic measurement instruments.
  • •Problem-Solving Support: Provided one-on-one assistance to students facing difficulties in circuit analysis, troubleshooting experimental setups, and understanding complex concepts such as Kirchhoff's laws, Thevenin/Norton equivalents, and frequency response analysis.
  • •Measurement Techniques: Taught students proper measurement methodologies including voltage/current measurements, waveform analysis, frequency measurements, impedance characterization, and component testing.
  • •Experimental Design & Verification: Guided students through the complete experimental process from circuit breadboarding and component placement to data collection, analysis, and result verification against theoretical predictions. Emphasized importance of error analysis and measurement uncertainty.
  • •Safety & Best Practices: Ensured laboratory safety protocols were followed, taught proper handling of electronic components, explained ESD protection measures, and demonstrated professional circuit debugging techniques.
  • •Assessment & Feedback: Evaluated student lab reports, provided constructive feedback on experimental procedures and data analysis, and assisted in grading practical examinations.

Laboratory Experiments Covered

Ohm's Law VerificationKVL & KCL AnalysisThevenin's TheoremNorton's TheoremSuperposition TheoremRC/RL TransientsRLC ResonanceDiode CharacteristicsBJT CharacteristicsCommon Emitter AmplifierFrequency ResponseTwo-Port Networks

Skills Developed

Teaching & MentoringLaboratory ManagementTechnical CommunicationProblem DiagnosisInstrumentationCircuit DebuggingStudent Assessment

Achievements

Recognition and milestones in my academic journey

GATE Qualification 2024-2025

Successfully qualified GATE in 2024-2025, one of India's most competitive examinations for postgraduate admissions in engineering and technology.

JEE Advanced Qualification

Successfully qualified and cleared JEE Advanced in 2020, demonstrating mastery in advanced engineering concepts.

JEE Mains Success

Achieved 94 percentile in JEE Mains, demonstrating competitive performance in one of India's most challenging engineering entrance examinations.

MHT-CET Excellence

Secured an impressive 99.30 percentile in the Maharashtra Common Entrance Test (MHT-CET), showcasing strong understanding of core engineering subjects.

First Rank in SSC Board Exams

Achieved first rank in school during the Secondary School Certificate (SSC) board examinations, demonstrating academic excellence and dedication to studies.

Leadership & Extracurricular

Beyond technical skills - teamwork and leadership experience

Rangawardhan

Chief Executive Officer• Spring 2021-22

Led and managed the Marathi Cultural Committee. Organized and managed 'Kawadasa' drama competition with participation from 5-6 colleges. Successfully planned and executed a 3-day cultural fest.

  • •Led Marathi Cultural Committee
  • •Organized inter-college drama competition
  • •Managed 3-day cultural fest

Society of Robotics and Automation (SRA)

Active Member• March 2023

Participated in various competitions. Built line following and self-balancing robots. Collaborated with team members on robotics projects.

  • •Built line following robots
  • •Developed self-balancing robots
  • •Participated in robotics competitions

Technical Club

Member• March 2023

Actively participating in technical workshops and events. Contributing to club's technical projects and initiatives.

  • •Technical workshops participation
  • •Contributing to technical projects
  • •Active in club initiatives

National Cadet Corps (NCC)

Cadet• 2014 - 2016

Secured A+ grade in Grade A examination. Developed leadership skills, discipline, and patriotism through rigorous training. Participated in various camps and community service activities.

  • •A+ grade in Grade A examination
  • •Leadership and discipline training
  • •Community service participation